Mentor Graphics Corp. has announced HyperLynx 7.5, the latest version of its tool suite for pre- and post-layout signal integrity (SI) simulation and analysis.
 HyperLynx 7.5 includes productivity and technology enhancements targeted at emerging SERDES interconnect standards such as PCI-Express, Hyper Transport, XAUI and SATA/SAS. The enhancements include the intuitive ‘free-form’ transmission-line schematic editor for pre-layout what-if exploration and design constraint development, enabling instantiation of SPICE and S-parameter models. All sources of signal loss are accounted for, including package parasitics, connector and via loss, as well as resistive and dielectric loss on the printed circuit board.
mentor.com
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HyperLynx 7.5 includes productivity and technology enhancements targeted at emerging SERDES interconnect standards such as PCI-Express, Hyper Transport, XAUI and SATA/SAS. The enhancements include the intuitive ‘free-form’ transmission-line schematic editor for pre-layout what-if exploration and design constraint development, enabling instantiation of SPICE and S-parameter models. All sources of signal loss are accounted for, including package parasitics, connector and via loss, as well as resistive and dielectric loss on the printed circuit board.
